Modern microprocessors may support the execution of complex instructions by converting them into a group of simpler instructions. The resulting group of simpler instructions may be called a “flow”. There may be flows consisting of micro-operations and described by microcode. These flows may be called microcode flows. There may also be flows whose conversion into a group of simpler instructions may be performed by a set of hardware logic. These flows may be called hardware flows. A processor may first decode the instruction into a microcode flow or a hardware flow, and then schedule the resulting microcode flow for execution on one or more execution units.
The execution units of a processor may be of varying types. For example, one processor may include one or more of the following types of execution units in its architecture: integer arithmetic, floating-point arithmetic, multimedia arithmetic, branch calculations and control; and memory load/store. Generally a microcode flow or a hardware flow representation of an instruction will be targeted to execute on one of these types of execution unit. However, often the targeted execution unit is not available or at least less available than others. The reason it may be not available or less available may be as simple as that execution unit is currently executing another flow corresponding to another instruction. But in some cases the targeted execution unit may be less available because it is turned off as a result of the processor entering a reduced power mode. To execute the microcode flow or hardware flow, the processor must first emerge from such a reduced power mode. In some cases, the targeted execution unit may be less available or not available due to a soft or hard failure. Each of these situations raises issues for the execution of the microcode flow or hardware flow representation of the instruction.